For high-speed digital electronics that may be used for wireless communications or other application, non-volatile memories are used. Non-volatile memories, such as resistive random access memory (ReRAM) and phase-change random access memory (PCRAM), however, have limited write endurance. Write endurance can be defined as the number of program/cycles that can be applied to a block of memory before the storage media becomes unreliable, and is usually calculated by estimating how often and how thoroughly the memory is used. In other words, write endurance measures the service life of a certain type of storage media.
Wear-leveling is a technique that is used to prolong the write endurance (e.g., service life) of storage media, and is part of cache design. One wear-leveling approach arranges data so that re-writes are evenly distributed across the storage medium. In this way, no single block fails due to a high concentration of write cycles. Other approaches to wear-leveling may include dynamically updating a map every time a write occurs, the map subsequently linking the written block to a new block. Another approach statically keeps the blocks the same without replacing them, but periodically rotates the blocks so they may be used by other data.
Wear-leveling for non-volatile memories (e.g., which may also be used in the main memories for computers) is well known and well explored. Nevertheless, when using wear-leveling for on-chip caches, traditional wear-leveling approaches that are usually employed for non-volatile memories exhibit too much performance overhead. Therefore, the high performance overhead inhibits the effectiveness of year-leveling techniques for caches having limited write endurance.